• Krivi offers state-of-art DDR PHY with DFI compatibility and minimum integration overheads. Our enterprise class PHY offers up to 4 chip select with independent training on each of them. Our patented jitter tolerant training algorithms and dynamic self-training ensures robust operation in presence of significant jitter and VT variations. PHY handles all the complex timing relationship and electrical specification required for successful DRAM operation.
    Synthesizable RTL along with superior analog DLL and propriety implementation flow enables meeting all the critical timing requirements with relative ease. It offers simple SoC integration by using DFI interface alone and limiting number of APB register programming requirements. All the critical timing paths are verified in SPICE with annotated power supply noise. Our digital verification environment models every possible uncertainty and jitter in the DDR system including PCB and DRAM.
    Our simplified SoC integration, easy implementation and robust verification methodology minimizes silicon risk and thus allows accelerated time to market at optimum budget.

Key Highlights:

  • DDR3/3L combo PHY GDS available in 28nm working at 2133Mbps
  • DDR3/4 and LPDDR2/3/4 PHY under development
  • Proven architecture with 15 years of experience
  • Simplified solution to SoC
    • Need only DFI interface and few register programming
    • Customized for every SoC if needed
  • Enterprise-class DDR PHY in consumer-class PHY area and power
  • State-of-art designs that works at top speeds with industry leading PPA
  • Patented Jitter tolerant digital training algorithms
    • Fail-safe write leveling for up to 1.7xTclk in presence of massive jitter
    • Jitter trap free READ and WRITE eye centering and de-skewing
    • Gate training for optimum pre-amble centering
  • Superior Analog components and IO pads
    • Analog DLL with 1.410 delay step
    • Shallow analog DLL for per-bit-deskew
    • Duty cycle corrector and sensor
    • Area and ESD optimized JEDEC compatible IO pads
    • De-skew PLL with competitive jitter
  • Tailored low power modes for SoC and DDR3 SDRAM
  • Comprehensive verification methodology
  • Up to 4 rank support with optional individual or shared training
  • High tolerance to voltage and temperature drifts and auto adaptation
  • Self-loopback BIST, at-speed ATPG and standalone I/O test
  • Simplified packaging

IO Pads

Krivi has vast experience in developing IO PAD libraries and many of the popular consumer devices use IO pads designed by Krivi’s core Team in previous companies. We offer almost every IO pads that you will need on built-to-order in addition to our available libraries. Discuss with us to get most area optimized library for your next SoC. You will pleasantly surprised to know about capabilities and PPA. Our robust ESD design is verified with in-house developed network SPICE simulations using foundry data.


We are offer industry’s leading DDR IO pad library. Our architectures have been verified across multiple foundries at different technology nodes. Novel architectures are used to get better PPA compared to available free libraries. Circuit level techniques are implemented to control SSO noise and Signal Integrity issues. This helps in reducing over-all cost for your product development and enables faster time to market.
Krivi offers multiple DDR standard compatibility through single IO pad. We support DDR3/4 and LPDDR2/3 standards through single IO pad.
We provide IBIS models with IO pad library and all the DDR IO’s are fully compliant to JEDEC standards. Features like retention without core-supply and power sequence independence are included in the design. ESD is enhanced with SPICE simulations.

  • Key Highlights:

    • 28nm DDR3/3L GDS available
    • Leading PPA in industry
    • Multi-standard IO pads
    • Easy to integrate
    • Low PAD Capacitance, Jitter and SSO noise
    • Minimal Duty Cycle variation
    • Robust ESD solution
    • IBIS Models
    • KRIVI 28nm DQ pad

Universal DDR IO Pad – Download PDF


KRIVI’s LVDS IO supports up to 2Gbps operation with receiver operating at rail to rail common mode. Our LVDS library offers optional in-built Bandgap reference generator and bias cell for controlling common mode of transmitter. These high speed bus drivers and receivers are compliant with the TIA/EIA-644-A standard for electrical characteristics of Low Voltage Differential Signaling (LVDS) interface circuits.

Key Highlights:

  • Low power and High Performance
  • Internal Band gap
  • Option to select external resistance to minimize power
  • Robust ESD solution
  • Library supports both wire-bond and flip-chip packaging

LVDS IO Pad – Download PDF